搜索资源列表
PLL-and-FLL-in-digital-costas-loop
- 锁相环和锁频环在数字costas环中的应用.pdf 一篇关于costa环路的新颖设计方案，包含大量的仿真图和性能分析，对学习锁相环有很大帮助-And frequency-locked loop PLL digital costas loop in the application. Pdf a novel about the costa loop design, contains a large number of simulation map and performance analysis a
Phase-Locked-Loop-FAQ
- 关于锁相环设计经常遇到的一些问题的官方解答.为设计者提供一些参考.-PLL design on some of the problems often encountered in the official answer. Provide some reference for the designer.
PLL
- 设计一个LabVIEW的锁相环程序，实现频率跟踪。-LabVIEW program to design a phase-locked loop to achieve a frequency tracking.
setup_pll_design
- PLL设计仿真，验证工具，这是一个很不错的软件-PLL design simulation
PLL
- 这是基于VHDL设计的PLL的国外文献，很详细的介绍的PLL如何设计，对初学者帮助很大！-This is the VHDL design of PLL based on foreign literature, how to design a very detailed introduction of the PLL, very helpful for beginners!
classic_PLL
- 非常经典的PLL设计讲义，清华大学重点实验室精华总结-PLL design PPT
digital-PLL
- 收集的关于数字锁相环的理论模型和分析讨论，适用于FPGA的数字电路设计。-Theoretical models and analysis and discussion about digital PLL collected for FPGA-based digital circuit design.
Weard-Saoud
- reseach about PLL design in Arabic
PLL_Design_Script
- PLL设计Matlab脚本，使用频域模型进行，希望有用-PLL Design Using MATLAB
designsteps
- matlab pll design and simulation,classical example.
PLL-signal-generator
- 0170、基于PLL信号发生器的设计论文资料-0170, based on the PLL signal generator design
pll
- 一个基于FPGA的载波同步环的设计，开发语言Verilog，开发工具ISE 14.7，可用于FM接收机中，典型SDR项目-An FPGA-based carrier synchronization loop design, development language Verilog, development tools ISE 14.7, FM receivers can be used, typically SDR project
XAPP879---PLL
- 基于FPGA的PLL锁相环设计资料，能给FPGA提供稳定的工作时钟，很好的资源啊！-FPGA based PLL to design information, give FPGA clock to provide a stable work, good resource ah!
pll
- ppl锁相环的设计-ppl The design of phase-locked loop
微信的FOC方案_AN1299
- 微 芯的FOC方案，这是使用PLL锁相环设计的，比1078的反正切要好(FOC scheme, which is the use of PLL phase-locked loop design, is better than 1078 point anyway)
CPPLL_SystemDesign
- 3阶电荷泵PLL的系统参数设计，以及系统响应特性验证(system design and verification of 3-order charge pump PLL)
zip
- 基于序阻抗的直驱风电场次同步振荡分析与锁相环参数优化设计((impedance modeling +PLL modeling) sequence impedance of direct drive wind power farm subsynchronous oscillation analysis and parameter optimization design based on PLL)
TSEK03_2017_T5_PLL
- Good source to design PLLs.
Hittite_PLL_Design_1p15_web
- 锁相环环路配置，用于迅太的产品，环路数值计算精准。(PLL loop filter design)
锁相环频率合成
- 基于51单片机的锁相环频率合成器的设计。使用PLL集成芯片CD4046，可编程分频芯片CD4522（同MC14522），使用LCD1602显示，频率由按键输入。标准输入信号为1khz方波。(Design of PLL Frequency Synthesizer Based on 51 single chip microcomputer. Using PLL integrated chip CD4046, programmable frequency division chip CD4522 (M